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A USB 3.0 readout system for Timepix3 detectors with on-board processing capabilities

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Author list: Dreier, Till;Fröjdh, Christer;Krapohl, David;Lawal, Najeem;Schöwerling, Jan Oliver

Publication year: 2018

ISSN: 1748-0221

DOI: http://dx.doi.org/10.1088/1748-0221/13/11/C11017

View additional information: View in Web of Science


Abstract

Timepix3 is a high-speed hybrid pixel detector consisting of a 256 x 256 pixel matrix with a maximum data rate of up to 5.12 Gbps (80 MHit/s). The ASIC is equipped with eight data channels that are data driven and zero suppressed making it suitable for particle tracking and spectral imaging.

In this paper, we present a USB 3.0-based programmable readout system with online preprocessing capabilities. USB 3.0 is present on all modern computers and can, under real-world conditions, achieve around 320MB/s, which allows up to 40 MHit/s of raw pixel data. With on-line processing, the proposed readout system is capable of achieving higher transfer rate (approaching Timepix4) since only relevant information rather than raw data will be transmitted. The system is based on an Opal Kelly development board with a Spartan 6 FPGA providing a USB 3.0 interface between FPGA and PC via an FX3 chip. It connects to a CERN T imepix 3 chipboard with standard VHDCI connector via a custom designed mezzanine card. The firmware is structured into blocks such as detector interface, USB interface and system control and an interface for data pre-processing. On the PC side, a Qt/C++ multi-platformsoftware library is implemented to control the readout system, providing access to detector functions and handling high-speed USB 3.0 streaming of data from the detector.

We demonstrate equalisation, calibration and data acquisition using a Cadmium Telluride sensor and optimise imaging data using simultaneous ToT (Time-over-Threshold) and ToA (Timeof- Arrival) information. The presented readout system is capable of other on-line processing such as analysis and classification of nuclear particles with current or larger FPGAs.


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